While setting the aggressive milestones for commercial silicon of SHAKTI and VEGA and their design wins by December 2023, Chandrasekhar mentioned that DIR-V will see partnerships between start-ups, academia and multinationals.
New Delhi: With an aim to enable creation of microprocessors for the future in India and towards realising the ambition of self-reliance, Union Minister of State for Electronics and Information Technology Rajeev Chandrasekhar on Wednesday announced the Digital India RISC-V Microprocessor (DIR-V) Program.
While setting the aggressive milestones for commercial silicon of SHAKTI and VEGA and their design wins by December 2023, Chandrasekhar mentioned that DIR-V will see partnerships between start-ups, academia and multinationals, to make India not only a RISC-V talent hub for the world but also a supplier of RISC-V SoC (System on Chips) for servers, mobile devices, automotive, IoT and microcontrollers across the globe.
Reminiscing his early days as x-86 processor chip designer at Intel, Chandrasekhar mentioned that many new processor architectures have gone through an initial period of ferment characterised by waves of innovations. At some point, however, they all settled on a dominant design. ARM and x-86 are two such instruction set architectures — one of which is licensed and other is sold, where industry consolidated in earlier decades.
However, RISC-V has emerged as a strong alternative to them in the last decade, having no licensing encumbrances, enabling its adoption by one and all in the semiconductor industry, at different complexity levels for various design purposes.
Challenging the status quo, RISC-V Instruction Set Architecture (ISA) is not only witnessing a quantum leap and unprecedented levels of processor innovation owing to its free and open nature but also pushing the Moore’s Law beyond its limits.
Today, there is a thriving ecosystem of chip designers at academia, scientific societies and start-ups in the country, contending to gain the market share in RISC-V’s growing market. While India has certainly taken several early steps in the processor design area, the time is felicitous now to advocate India’s strides in RISC-V global community and unveil the Digital India RISC-V Processor roadmap to the world.
India, today, announces its ambitious roadmap with Ministry of Electronics and IT planning to join the RISC-V International as Premiere Board Member to collaborate, contribute and advocate India’s expertise with other global RISC-V leaders.
Chandrasekhar announced the DIR-V Program with Prof V Kamakoti, Director, IIT Madras, as the Chief Architect and S Krishnakumar Rao as the programme manager. He also unveiled not only the blueprint of the roadmap of the design and the implementation of the DIR-V Program with – SHAKTI Processor by IIT Madras and VEGA Processor by C-DAC but also the strategic roadmap for India’s semiconductor design and Innovation to catalyse the semiconductor ecosystem in the country.
RISC-V ISA, being available in open-source, Dr Rajendra Kumar, Additional Secretary and Arvind Kumar, Group Coordinator (R&D in Electronics), MeitY, projected its growth potential and mentioned that RISC-V will pave the way for the next decade of computing design and innovations and adoption in the future generation of processors.
Bob Brennan, VP, Intel Foundry Services, while speaking about IFS (Intel Foundry Services) Innovation Fund announced by Intel to support early stage start-ups and established companies building disruptive technologies for the foundry ecosystem, appreciated the Indian RISC-V movement.
Kamakoti, while highlighting Intel’s support for getting the 22 mm SHAKTI Chip fabricated at the Intel foundry, mentioned that the DIR-V Program will catalyse the design innovation in the country and will encourage several domestic start-ups working in RISC-V domains like micro architecture design, verification and security aspects.
Naveed Sherwani, Chairman, RapidSilicon was of the view that with India joining the RISC-V International, the Global Open Source Hardware revolution will get a new leap forward.
Calista Redmond, CEO, RISC-V International, highlighted the profound technical collaboration in RISC-V community by IIT Madras, one of five honoured RISC-V development partners. She also congratulated C-DAC for designing a range of RISC-V processors and InCore Semiconductors for releasing the Open-Source RISC-V Core Verification tool.